2021 Symposia on VLSI Technology and Circuits

Imec will be present at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021) with as many as 21 accepted papers, papers – 15 in VLSI Technology, 2 in VLSI Circuits and 4 in the Technology/Circuit Joint sessions. These papers include 2 invited papers, by Dr. Eric Beyne, 3D systems program director, and by Dr. Iuliana Radu, quantum and exploratory computing program director, showing its strong capabilities in logic, memory, 3D, power, qubit devices and more. The invited papers are on (1) design and technology solutions for 3D system integration, and on (2) progress on 300mm fabrication of qubit devices and on classical CMOS components to enable the quantum system. In several papers, imec also reports progress in developing enabling technologies for a backside power delivery network: the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices, new approaches for efficient power delivery and conversion that are compatible with backside processing and the impact of backside connection on I/O performance from a system-technology co-optimization (STCO) perspective.

Next to these papers, Naoto Horiguchi, logic CMOS scaling program director, will speak at the Technology Short Course on nanosheet device architectures, and Marcel Zevenbergen, smart agrifood program manager, will speak at the Circuits Short Course on non-CMOS based sensors for IoT.

Imec will also host a workshop on the state-of-the-art of 3D IC technology, design techniques and application, given by Dr. Rongmei Chen, research scientist and Dr. Geert Van der Plas, 3D system integration program manager.

Invited papers

• Design and Technology Solutions for 3D Integrated High Performance Systems
  Geert Van der Plas and Eric Beyne
• Solid State Qubits: How Learning from CMOS Fabrication Can Speed-Up Progress in Quantum Computing
  Iuliana Radu

Imec highlights

In this paper, imec presents for the first time an electrical characterization of its forksheet devices that were successfully integrated by using a 300mm process flow, with gate lengths down to 22nm.

• Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space
  Author: Hans Mertens, et al.
  
  Abstract
  We report on forksheet N- and PFETs co-integrated with gate-all-around nanosheet FETs. The forksheet short-channel control is on par with nanosheets down to 22nm gate length (SSSAT=66-68mV/dec). Forksheet ION and IOFF characteristics are improved by post-channel-release wet clean optimization, attributed to gate stack interface trap density reduction. Dual work function metal gates are integrated at 17nm N-P space, highlighting a key benefit of forksheets for CMOS area scaling.

In several papers presented at the 2021 Symposia on VLSI Technology and Circuits (VLSI 2021), imec reports progress in developing enabling technologies for a backside power delivery network. First, the impact of backside wafer processing on the performance of ‘frontside’ FinFET devices was investigated. Second, the team revealed new approaches for efficient power delivery and conversion that are compatible with backside processing. And finally, the impact of backside connection on I/O performance is discussed from a system-technology co-optimization (STCO) perspective.

• Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster
  Author: Anabela Veloso, et al.
  
  Abstract
  We report on scaled Si-channel finFETs (Lgate>=20nm, 45nm fin pitch) with backside connectivity enabled by extreme wafer thinning (several Si thicknesses under STI-oxide targeted: from ~370nm down to ~20nm) and W-filled nano-through-Si-vias (n-TSV) of various heights, after using low-temperature, wafer-to-wafer, dielectric bonding. This scheme aims at allowing decoupling signal and power networks, with reduced IR-drop predicted by moving the latter to the wafer backside. A thorough evaluation of the impact of 3D processing on device characteristics is presented, showing: 1) enhanced nmos mobility and drive currents (up to 15%); 2) for pmos, small ION loss (~3 to 10%), larger Rext, with channel strain evaluation by NBD for various layouts; 3) ΔVT~-130mV that can be recovered with an extra anneal at the end, keeping tight variability and matching control. No BTI degradation is observed, with further indication that the final anneal(s) selection can be beneficial for electrostatics and reliability improvement.
• Backside Power Delivery with a Direct 14:1/19:1 High-Ratio Point-of-Load Power Converter for Servers and Datacenters
  Author: Hesheng Lin, et al.
  
  Abstract
  For computing systems, a fully integrated backside power delivery with a direct 14:1/19:1-ratio power converter is presented featuring (1) backside laterally-diffused power MOS with 1.5x lower Qon*Ron and 4.9x lower output Coss compared to the stacked IO device, and (2) in-package optimized transformer with an innovative magnetic material (Bsat=0.77 T, coercivity=0.35 Oe, and resistivity>1e8 Ω∙cm). With a 14:1 conversion ratio and 166x boost in power per volume (vs discrete), the total power delivery efficiency is 72% at 1 W/mm2.
• 91.5%-Efficiency Fully Integrated Voltage Regulator with 86fF/um^2-High-Density 2.5D MIM Capacitor
  Author: Hesheng Lin, et al.
  
  Abstract
  We present a 91.5% power-delivery-efficiency for high performance computing (HPC) systems including a 1/2-ratio charge pump circuit with 2.5D MIM capacitor. With high capacitance density (86 fF/μm2 , 1.36-V bias/10 year/100°C), 0.1% parasitic impact, and small form factor (~μm thick), this MIM solution enables converters with high ratio (up to 1/5 with 82% efficiency), high power density (4.8 W/mm2 for ratio=1/3), low VOUT (0.7 V), and sub-ns transient response for HPC systems.
• External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options
  Author: Wen-Chieh Chen, et al.
  
  Abstract
  In this paper, the challenges of the I/O development roadmap are discussed. The impact of I/O application in FEOL scaling and 3D integration are evaluated. A cost-efficient circuit solution to the I/O implementation in a gate-all-around (GAA) nanosheet (NS) technology is proposed. The functionality verification and the relevant reliability concerns are assessed in a mature industrial CMOS process. Finally, to foresee the design strategies in future STCO scaling era, the impact of the fully back-side (BS) connections on I/O performance is investigated. Capacitance is doubled compared to front-side (FS) I/O due to the contributions from BS connection layers. The layout techniques can mitigate ~30% of the extra capacitance and the technology option of the deep trench isolation (DTI) is considered to reduce the extra capacitance to only ~8%.

2021 Symposium on VLSI Technology and Circuits Program

Sunday, June 13

Workshop 2

PPAC Analysis and System-Technology Co-Optimization for 3D Memory-on-Logic IC, Many-Core SOC and AI Computing Applications - Rongmei Chen and Geert Van der Plas

Monday, June 14

Short Course 1 (Technology) - Advanced Process and Device Technology Toward 2nm-CMOS and Emerging Memory

• Nanosheet Device Architectures to Enable CMOS Scaling in 3nm and Beyond: Nanosheet, Forksheet and CFET - Naoto Horiguchi

Short Course 3 (Circuits) Advanced Circuits and Systems for Internet-of-Things (IoT) Sensors

• Non-CMOS Based Sensors for IoT - Marcel Zevenbergen

Tuesday, June 15

Session 2 – Highlight

Forksheet FETs for Advanced CMOS Scaling: Forksheet-Nanosheet Co-Integration and Dual Work Function Metal Gates at 17nm N-P Space - Hans Mertens, et al.

Session 3 – Future Logic Devices

Scaling synthetic WS2 dual-gate MOS devices towards sub-nm CET - Dennis Lin, et al.

High yield and process uniformity for 300 mm integrated WS2 FETs - Tom Schram, et al.

Wednesday, June 16

Technology Focus Session 2 - New Process and Material for Future Devices

Low Temperature Atomic Hydrogen Treatment for Superior NBTI Reliability-Demonstration and Modeling across SiO2 IL Thicknesses from 1.8 to 0.6 nm for I/O and Core Logic - Jacopo Franco, et al.

Enabling Logic with Backside Connectivity via n-TSVs and its Potential as a Scaling Booster - Anabela Veloso, et al.

Thursday, June 17

Technology / Circuits Joint Focus Session 1 - 3D/Heterogeneous Integration

Design and Technology Solutions for 3D Integrated High Performance Systems - Geert Van der Plas and Eric Beyne

Session 8 - 3D Flash Memory

First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D-NAND Memory Devices - Arjun Ajaykumar, et al.

Session 9 - Power Device

Backside Power Delivery with a Direct 14:1/19:1 High-Ratio Point-of-Load Power Converter for Servers and Datacenters - Hesheng Lin, et al.

91.5%-Efficiency Fully Integrated Voltage Regulator with 86fF/um^2-High-Density 2.5D MIM Capacitor - Hesheng Lin, et al.

Session 10 - IGZO Transistor and III-V Device

First demonstration of sub-12 nm Lg gate last IGZO-TFTs with oxygen tunnel architecture for front gate devices - Subhali Subhechha, et al.

Additional Q&A Session

High Yield and Process Uniformity for 300 mm Integrated WS2 FETs - Tom Schram, et al.

Enabling Logic with Backside Connectivity Via n-TSVs and Its Potential as a Scaling Booster - Anabela Veloso, et al.

First Demonstration of Sub-12 nm Lg Gate Last IGZO-TFTs with Oxygen Tunnel Architecture for Front Gate Devices - Subhali Subhechha, et al.

Friday June 18

Technology / Circuits Joint Focus Session 2 – Computing-in-Memory

Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications - Daisuke Saito, et al.

Session 11 - SOT-MRAM

BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning - Sebastien Couet, et al.

Multi-pillar SOT-MRAM for Accurate Analog in-Memory DNN Inference - Jonas Doevenspeck, et al.

Graphene electro-absorption modulators integrated at wafer-scale in a CMOS fab - ChengHan Wu, et al.

Session 13 - Neural Interface Circuits and Systems

A 77-dB DR 16-Ch 2nd-Order Δ-ΔΣ Neural Recording Chip with 0.0077mm2 /Ch - Shiwei Wang et al.

Session 15 High-Speed ADCs

A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS - Jorge Lagos, et al.

A Compact 8-bit 8 GS/s 8xTI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW - Ewout Martens, et al.

An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC - Lai Wei

Saturday June 19

Forum: Technologies for Post COVID-19 Era

Leveraging Semiconductor Technologies for Next-Generation Healthcare Tools - Peter Peumans

Session 15 - Nanosheet and DTCO

External I/O interfaces in sub-5nm GAA NS Technology and STCO Scaling Options - Wen-Chieh Chen, et al.

Technology / Circuits Joint Focus Session 5 Circuit and Technology for Quantum Computing

Solid State Qubits: How Learning from CMOS Fabrication Can Speed-Up Progress in Quantum Computing - Iuliana Radu, et al.

Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process - Nard Dumoulin Stuyck, et al.

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